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| SAT Mixer-Oscillator-PLL for 3.3 GHz TUA 6110XS Features q q q q q q q q q q q q q q q q q Smallest possible lock-in time; no asynchronous divider stage 1-chip system for MPU control (I2C Bus) Fast I2C Bus mode possible 4 programmable chip addresses Short pull-in time for quick channel switch-over and optimized loop stability P-SSOP-28-1 3 high-current switch outputs 2 TTL inputs 5-level A/D converter Lock-in flag Power-down flag Few external components Frequency and amplitude-stable balanced oscillator for the Band A and Band B frequency range Optimum decoupling of input frequency from oscillator Double balanced mixer with wide dynamic range and low-impedance inputs for the Band A and Band B frequency range Internal band switch Low-noise reference voltage Package P-SSOP-28-1 Type w TUA 6110XS w New type Application Ordering Code Q67000-A5211 Package P-SSOP-28-1 The IC is suitable for all SAT-Tuners in TV-VCR-Sets and TOPSET-Converters. Semiconductor Group 1 04.96 TUA 6110XS Pin Configuration (top view) P-SSOP-28-1 Figure 10 Pin Definitions and Functions PLL Section Pin No. 6 9 10 11 12 13 14 15 16 17 18 19 Symbol CAS GNDD SDA SCL Function Chip address select Ground for digital block (PLL) Data input/output for the I2C Bus Clock input for the I2C Bus Positive supply voltage for digital block (PLL) 4 MHz low-impedance crystal oscillator input 4 MHz low-impedance crystal oscillator input Port output/ADC input Port output/TTL input Port output/TTL input Open collector output for pull up resistor/loop filter 2 VVCCD Q Qx P2/ADC P1/I1 P0/I0 TUNE CHGPMP Charge pump output/loop filter Semiconductor Group TUA 6110XS Mixer-Oscillator Section Pin No. 1 2 3 4 5 7 8 20 21 22 23 24 25 26 27 28 Symbol MIXA MlXAx MIXB MlXBx Function Band A mixer input, low-impedance, symmetrical to MlXAx Band A mixer input, low-impedance, symmetrical to MIXA Band B mixer input, low-impedance, symmetrical to MlXBx Band B mixer input, low-impedance, symmetrical to MlXB Positive supply voltage for analog block Open collector mixer output, high-impedance, symmetrical to IFx Open collector mixer output, high-impedance, symmetrical to IF Ground for analog block Band B oscillator amplifier, high-impedance base input, symmetrical to OB-B2 Band B oscillator amplifier, low-impedance emitter output, symmetrical to OB-E2 Band B oscillator amplifier, low-impedance emitter output, symmetrical to OB-E1 Band B oscillator amplifier, high-impedance base input, symmetrical to OB-B1 Band A oscillator amplifier, high-impedance base input, symmetrical to OA-B2 Band A oscillator amplifier, low-impedance emitter output, symmetrical to OA-E2 Band A oscillator amplifier, low-impedance emitter output, symmetrical to OA-E1 Band A oscillator amplifier, high-impedance base input, symmetrical to OA-B1 VVCCA IF IFx GNDA OB-B1 OB-E1 OB-E2 OB-B2 OA-B1 OA-E1 OA-E2 OA-B2 Semiconductor Group 3 TUA 6110XS Figure 11 Block Diagram Semiconductor Group 4 TUA 6110XS Functional Description The TUA 6110X device combines a digitally programmable phase locked loop (PLL), with a mixer-oscillator block including two balanced mixers and oscillators for use in SAT tuners. The PLL block with four hard-switched chip addresses, forms a digitally programmable phase locked loop. With a 4 MHz quartz crystal, the PLL permits precise setting of the frequency of the sattuner oscillator up to 3.3 GHz in increments of 125 kHz. The tuning process is controlled by a microprocessor via an I2C Bus. The device has three output ports, which all can also be used as input ports (two TTL inputs and one A/D converter input). A flag is set when the loop is locked. The input ports and lock flag can be read by the processor via the I2C Bus. The mixer-oscillator block includes two balanced mixers (double balanced mixer with low-impedance input), two frequency and amplitude-stable balanced oscillators for Band A and Band B, a low-noise reference voltage source and a band switch. Semiconductor Group 5 TUA 6110XS Circuit Description General Description Mixer-Oscillator Block The mixer-oscillator section includes two balanced mixers (double balanced mixer), two balanced oscillators for Band A and Band B, a reference voltage source and a band switch. The band switch ensures that only one mixer-oscillator block at a time is activated. In the activated band the signal passes a frontend stage with MESFET amplifier, a doubletuned bandpass filter and is then fed to the balanced mixer input of the IC which has a low-impedance input. The input signal is mixed there with the on chip oscillator signal from the activated oscillator section. PLL Block The mixer-oscillator signal VCO/VCOx is internally DC-coupled as a differential signal at the programmable divider inputs. The signal subsequently passes through a programmable divider with ratio N = 256 through 32767 and is then compared in a digital frequency/phase detector to a reference frequency fREF = 125 kHz. This frequency is derived from a balanced, low-impedance 4 MHz crystal oscillator (pin Q, Qx) divided by Q = 32. The phase detector has two outputs UP and DOWN that drive two current sources l+ and I- of a charge pump. If the negative edge of the divided VCO signal appears prior to the negative edge of the reference signal, the l+ current source pulses for the duration of the phase difference. In the reverse case the I- current source pulses. If the two signals are in phase, the charge pump output (CHGPMP) goes into the high-impedance state (PLL is locked). An active low-pass filter integrates the current pulses to generate the tuning voltage for the VCO (internal amplifier, external pullup resistor at TUNE and external RC circuitry). The charge pump output is also switched into the high-impedance state when the control bit T0 = 1. Here it should be noted, however, that the tuning voltage can alter over a long period in the high-impedance state as a result of self-discharge in the peripheral circuity. TUNE may be switched off by the control bit OS to allow external adjustments. By means of a control bit 5I the pump current can be switched between two values by software. This programmability permits alteration of the control response of the PLL in the locked-in state. In this way different VCO gains can be compensated, for example. Semiconductor Group 6 TUA 6110XS The software-switched ports P0, P1, and P2 are general-purpose open-collector outputs. The test bit T1 = 1, switches the test signals fREF (4 MHz/32) and Cy (divided input signal) to P0 and P1 respectively. P0, P1, and P2 are bidirectional: P0 and P1 are TTL inputs; P2 is an A/D converter input. Data are exchanged between the processor and the PLL via the I2C Bus. The clock is generated by the processor (input SCL), while pin SDA functions as an input or output depending on the direction of the data (open collector, external pull-up resistor). Both inputs have hysteresis and a low-pass characteristic, which enhance the noise immunity of the I2C Bus. The data from the processor pass through an I2C Bus controller. Depending on their function the data are subsequently stored in registers. If the bus is free, both lines will be in the marking state (SDA, SCL are HIGH). Each telegram begins with the start condition and ends with the stop condition. Start condition: SDA goes LOW, while SCL remains HIGH. Stop condition: SDA goes HIGH while SCL remains HIGH. All further information transfer takes place during SCL = LOW, and the data is forwarded to the control logic on the positive clock edge. The table 3 `Bit Allocation' should be referred to the following description. All telegrams are transmitted byte-by-byte, followed by a ninth clock pulse, during which the control logic returns the SDA line to LOW (acknowledge condition). The first byte is comprised of seven address bits. These are used by the processor to select the PLL from several peripheral components (chip select). The eighth bit (R/W) determines whether data are written into (R/W = 0) or read from (R/W = 1) the PLL. In the data portion of the telegram during a WRITE operation, the first bit of the first or third data byte determines whether a divider ratio or control information is to follow. In each case the second byte of the same data type or a stop condition has to follow the first byte. If the address byte indicates a READ operation, the PLL generates an acknowledge and then shifts out the status byte onto the SDA line. If the processor generates an acknowledge, a further status byte is output; otherwise the data line is released to allow the processor to generate a stop condition. The status word consists of two bits from the TTL input ports, three bits from the A/D converter, the lock flag and the power-on flag. Four different chip addresses can be set by appropriate connection of pin CAU (see table 4 `Address Selection'). When the supply voltage is applied, a power-on reset circuit prevents the PLL from setting the SDA line to LOW, which would block the bus. The power-on reset flag POR is set at power-on and when VVCCD goes below 3.2 V. It will be reset at the end of a READ operation. Semiconductor Group 7 TUA 6110XS The lock detector resets the lock flag FL when the width of the charge pump current pulses is greater than the period of the crystal oscillator (i.e. 250 ns). Hence, when FL = 1, the maximum deviation of the input frequency from the programmed frequency is given by f = IP(Kvco / fQ) (C1 + C2) / (C1C2) where Ip is the charge pump current, KVCO the VCO gain, fQ the crystal oscillator frequency and C1, C2 the capacitances in the loop filter (see Application Circuit). As the charge pump pulses at 125 kHz (= fREF), it takes a maximum of 8 s for FL to be reset after the loop has lost lock state. Once FL has been reset, it is set only if the charge pump pulse width is less than 250 ns for eight consecutive fref periods. Therefore, it takes between 64 and 72 s for FL to be set after the loop regains lock. Table 3 Bit Allocation Read/Write Data MSB Write Data Address Byte Prog. Divider Byte1 Control Byte1 Control Byte 2 Read Data Address Byte Status Byte 1 POR 1 FL 0 x 0 I1 0 I0 MA1 A2 MA0 A1 1 A0 Ack Ack 1 0 1 A/B 1 n14 n6 5I x 0 n13 n5 T1 x 0 n12 n4 T0 x 0 n11 n3 1 x MA1 n10 n2 1 P2 MA0 n9 n1 1 P1 0 n8 n0 OS P0 Ack Ack Ack Ack Ack Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 LSB Ack Prog. Divider Byte 2 n7 Note: MSB is shifted first. Divider Ratio N = 16384 x n14 + 8192 x n13 + 4096 x n12 + 2048 x n11 + 1024 x n10 + 512 x n9 + 256 x n8 + 128 x n7 + 64 x n6 + 32 x n5 + 16 x n4 + 8 x n3 + 4 x n2 + 2 x n1 + n0 Semiconductor Group 8 TUA 6110XS Ports P0, P1, P2 1 0 Open-collector output is active Open-collector output is inactive, TTL-inputs I1, I0 and ADC available Bandswitch A/B High switch to OSC/MIX B Pump Current 5I High switch to high current Disabling Tuning Voltage OS High disables TUNE Power On Reset flag POR:flag is set at power-on and reset at the end of a READ operation PLL lock flag FL: flag is set when loop is locked TTL-inputs I1, I0: input data from pins P1/I1, P0/I0 Semiconductor Group 9 TUA 6110XS Table 4 Address Selection Voltage at CAS (0 ... 0.1) x VVCCD Open circuit (0.4 ... 0.6) x VVCCD (0.9 ... 1) x VVCCD Table 5 Test Modes Test Mode Normal operation P1 = Cy output, P0 = fREF output Charge pump output CHGPMP is in high-impedance state TTL-inputs I1/I0 are Cy/fREF inputs of phase detector Table 6 A/D Converter Levels Voltage at P2/ADC (0 ... 0.15) x VVCCD (0.15 ... 0.3) x VVCCD (0.3 ... 0.45) x VVCCD (0.45 ... 0.6) x VVCCD (0.6 ... 1) x VVCCD A2 0 0 0 0 1 A1 0 0 1 1 0 A0 0 1 0 1 0 T1 0 1 0 1 T0 0 0 1 1 M1 0 0 1 1 M0 0 1 0 1 Semiconductor Group 10 TUA 6110XS Figure 12 Circuit Description Semiconductor Group 11 TUA 6110XS Absolute Maximum Ratings TA = - 20 C to 80 C Parameter Symbol Limit Values Unit min. PLL Supply voltage Current Output CHGPMP Crystal oscillator pins Q, Qx Bus input/output SDA Bus input SCL Port outputs P0, P1, P2 Chip address switch CAU Output active filter TUNE Bus output SDA Port outputs P0, P1, P2 Total port output current Junction temperature Storage temperature Thermal resistance (junction to ambient) Mixer-Oscillator Supply voltage Current Output IF, IFX Operating Range Parameter Supply voltage Supply voltage Semiconductor Group Remarks max. VVCCD IVCCD VCHGPMP VQ VSDA VSCL VP VCAU VTUNE ISDAL IPL IPL - 0.3 - 0.3 - 0.3 - 0.3 - 0.3 - 0.3 - 0.3 - 0.3 -1 -1 +6 40 + 3.5 V mA V V V V V V V mA mA mA C C VVCCD +6 +6 + 13 VVCCD + 33 5 15 20 + 125 open collector open collector Tj TS RthA - 40 + 125 75 K/W VVCCA IVCCA IIF, IIFX - 0.3 +6 40 9 V mA mA open collector Symbol Limit Values Units Remarks min. max. + 5.5 + 5.5 V V + 4.5 + 4.5 VVCCD VVCCA 12 TUA 6110XS Operating Range Parameter Supply current Supply current Mixer output voltage Mixer output current Programmable divider factor Symbol Limit Values Units Remarks min. max. 35 35 + 5.5 8.0 32767 2050 2550 2300 3000 + 80 MHz MHz MHz MHz C IVCCD IVCCA VIF, IFX IIF, IFX 18 18 + 4.5 4.0 256 900 1700 1350 2250 - 20 mA mA V mA open collector open collector N Band A Mixer input frequency range fMA Band B Mixer input frequency range fMB Band A Oscillator frequency range fOA Band B Oscillator frequency range fOB Ambient temperature TA AC/DC Characteristics VVCCD = 4.5 V to 5.5 V; TA = - 20 C to 80 C Parameter PLL Supply current Symbol min. Limit Values typ. 26 max. 31 mA Units Test Condition IVCCD 21 VVCCD = 5 V Crystal Oscillator Connections Q, QX Crystal frequency Crystal resistance1) Oscillation frequency Drive current1) Input impedance Margin from 1st (fundamental) to 2nd and 3rd harmonics1) Notes see page 141. fQ RQ fQ IQ ZQ aH 3.2 10 4.0 4.8 100 MHz series resonance series resonance 3.99975 4.000 4.00025 MHz tbd - 600 tbd tbd 20 Arms fQ = 4 MHz fQ = 4 MHz fQ = 4 MHz fQ = 4 MHz - 750 - 900 dB Semiconductor Group 13 TUA 6110XS AC/DC Characteristics (cont'd) VVCCD = 4.5 V to 5.5 V; TA = - 20 C to 80 C Parameter Symbol min. Limit Values typ. max. Units Test Condition Charge Pump Output CHGPMP (VVCCD = 5 V) HIGH output current ICPH LOW output current Tristate current Output voltage 90 22 1.0 220 300 50 +1 2.5 75 A A nA V 5I = 1, VCP = 2 V 5I = 0, VCP = 2 V T0 = 1,VCP = 2 V locked ICPL ICPZ VCP Drive Output TUNE (open collector) HIGH output current ITH LOW output voltage 10 0.5 A V VTH = 33 V, T0 = 1 VTL ITL = 1.5 mA Port Outputs P0, P1, P2 (open collector) HIGH output current IPOH LOW output voltage 10 0.5 A V VPOL VPOH = 13.5 V IPOL = 15 mA TTL Port Inputs P0, P1 HIGH input voltage LOW input voltage HIGH input current LOW input current ADC Port Input P2 HIGH input current LOW input current VPIH VPIL IPIH IPIL 2.7 0.8 10 - 10 V V A A VPIH = 13.5 V VPIL = 0 V IADCH IADCL 10 - 10 A A Semiconductor Group 14 TUA 6110XS AC/DC Characteristics (cont'd) VVCCD = 4.5 V to 5.5 V; TA = - 20 C to 80 C Parameter Symbol min. Address Selection Input CAS HIGH input current LOW input current I2C Bus Bus inputs SCL, SDA HIGH input voltage LOW input voltage HIGH input current LOW input current Limit Values typ. max. Units Test Condition ICASH ICASL 50 - 50 A A VCASH = 5 V VCASL = 0 V VIH VIL IIH IIL 3 5.5 1.5 10 V V A A - 20 VIH = VS VIL = 0 V Bus Output SDA (open collector) HIGH output current IOH LOW output voltage 10 0.4 A V VOL VOH = 5.5 V IOL = 3 mA Edge Speed SCL, SDA Rise time Fall time Clock Timing SCL Frequency HIGH pulse width LOW pulse width tr tf 300 300 ns ns fSCL tH tL 0 0.6 1.3 400 kHz s s Semiconductor Group 15 TUA 6110XS AC/DC Characteristics (cont'd) VVCCD = 4.5 V to 5.5 V; TA = - 20 C to 80 C Parameter Symbol min. Start Condition Set-up time Hold time Stop Condition Set-up time Bus free Data Transfer Set-up time Hold time Input hysteresis SCL, SDA1) Noise immunity SCL, SDA1), 2) Capacitive load for each bus line Mixer-Oscillator Current consumption Mixer output impedance Limit Values typ. max. Units Test Condition tsusta thsta 0.6 0.6 s s tsusto tbuf 0.6 1.3 s s tsudat thdat Vhys VN CL 0.1 0 200 5 400 s s mV Vpp pF fN = 1 MHz ... 14 MHz IVCCA IVCCB RIF, IFX CIF, IFx 21 21 26 26 11 0.5 32 32 mA mA k pF Bit A/B = L Bit A/B = H Parallel equivalent circuit Parallel equivalent circuit 1) 2) Design note: no 100 % final inspection. Sinusoidal noise signal applied via 33 pF coupling capacitor. Semiconductor Group 16 TUA 6110XS AC/DC Characteristics (cont'd) VVCCD = 4.5 V to 5.5 V; TA = - 20 C to 80 C Parameter Symbol min. Band A Circuit Section Oscillator frequency range Oscillator drift Limit Values typ. max. Units Test Condition fOscA fOscA fOscA fOscA 1350 2550 2 2 5 MHz MHz MHz MHz Vd = 0 ... 28 V VS = 5 V 10 % T = 25 C t = 5 s up to 15 min. after switching on Oscillator pulling Mixer gain Mixer noise figure VMIXA VMIXA VMIXA VMIXA GMixA FMixA FMixA dBV f = tbd dBV f = tbd dBV fint = tbd dBV fint = tbd 3 6 9 15 25 10 20 9 dB dB dB nH dB fe = 950 MHz (DSB) fe = 2.1 GHz (DSB) serial equivalent circuit serial equivalent circuit Mixer input impedance RMixA LMixA IF suppression aIF VMixB = 80 dBV Semiconductor Group 17 TUA 6110XS AC/DC Characteristics (cont'd) VVCCD = 4.5 V to 5.5 V; TA = - 20 C to 80 C Parameter Symbol min. Band B Circuit Section Oscillator frequency range Oscillator drift fOscB fOscB fOscB fOscB 2.25 3.0 1 1 2 GHz MHz MHz MHz Limit Values typ. max. Units Test Condition Vt = 0 ... 28 V VS = 5 V 10 % T = 25 C t = 5 s up to 15 min. after switching on Oscillator pulling Mixer gain Mixer noise figure VMIXB VMIXB VMIXB VMIXB GMixB FMixB BV BV f = tbd f = tbd dBV fint = tbd dBV fint = tbd 3 15 18 dB dB dB nH dB fe = 2.0 GHz (DSB) fe = 2.5 GHz (DSB) serial equivalent circuit serial equivalent circuit Mixer input impedance RMixB LMixB 35 10 20 IF suppression aIF VMixB = 80 dBV Semiconductor Group 18 TUA 6110XS Test Circuit 1 Figure 13 Measurement of Crystal Oscillator Frequency Figure 14 Equivalent I/O-Schematic Semiconductor Group 19 TUA 6110XS Test Circuit 2 Figure 15 Measurement of S-Parameter S11, S12, S21, S22 and Calculation of -Equivalent Circuit Table 7 Test Frequency Test Point Mixer input impedance A Mixer input impedance B Test Frequency in MHz 950 2000 Pin x 1 3 Pin y 2 4 Semiconductor Group 20 TUA 6110XS Test Circuit 3 Figure 16 Measurement of Output Capacitance by Measurement of S-Parameters S11, S12, S21, S22 at 480 MHz Semiconductor Group 21 TUA 6110XS Test Circuit 4 Figure 17 Semiconductor Group 22 TUA 6110XS Equivalent I/O-Schematic Figure 18 Equivalent I/O-Schematic of Charge Pump Semiconductor Group 23 TUA 6110XS Figure 19 Equivalent I/O-Schematic of Port Pins Semiconductor Group 24 TUA 6110XS Figure 20 Equivalent I/O-Schematic of CAS Pin Figure 21 Equivalent I/O-Schematic of SDA/SCL Pins Semiconductor Group 25 TUA 6110XS Figure 22 Equivalent I/O-Schematic of MIXA / MIXAX / MIXB / MIXBX Pins Figure 23 Equivalent I/O-Schematic of Oscillator Pins Semiconductor Group 26 TUA 6110XS Figure 24 I2C Bus Timing Semiconductor Group 27 |
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